AD7606 Data Acquisition Module

Pin

Description

AVcc

Simulated voltage source, ranging from 4.75V to 5.25V

AGNG

Grounding

OS[2:0]

Over-sampling mode pin. Logical input. These inputs are used to select the over-sampling rate. OS2 is the MSB control bit, while OS0 is the LSB control bit.

PAR(Low level is active)/SER/BYTE SEL

Parallel/Serial/Byte interface selection input. If this pin is connected to a logic low level, then the parallel interface is selected. If this pin is connected to a logic high level, then the serial interface is selected.

RANG

Select the input range for analog input. If this pin is connected to a logic high level, the analog input range for all channels is +10V. If this pin is connected to a logic low level, the analog input range for all channels is +5V.

CONVST A / CONVST B

Activate the conversion signal. CONVST A activates channels 1, 2, 3, and 4; CONVST B activates channels 5, 6, 7, and 8.

RESET

Reset input. When set to a logic high level, the rising edge of RESET resets; the typical width of the high pulse of RESET is 50ns. If a RESET pulse is applied during the conversion, the conversion will be interrupted. If a RESET pulse is applied during the read operation, the content of the output register will be reset to 0.

RD(Low level is active)/SCIK

When choosing the parallel interface, it is the parallel data read control input (RD_); when choosing the serial interface, it is the serial clock input (SCLK). In parallel mode, if both CS_ and RD_ are at a logical low level, the output bus will be enabled. In serial mode, this pin is used as the serial clock input for data transmission. The falling edge of CS causes the data output lines DoutA and DoutB to exit the tri-state mode, and sequentially outputs the most significant bit (MSB) of the conversion result. The rising edge of SCLK sequentially transmits all subsequent data bits to the serial data output DoutA and DoutB. Reset input. When set to a logic high level, the rising edge of RESET resets; the typical width of the RESET high pulse is 50ns. If a RESET pulse is applied during the conversion, the conversion will be interrupted. If a RESET pulse is applied during the read operation, the content of the output register will be reset to 0.

CS

Chip Select. This low level signal is effective. In parallel mode, if both CS and RD are at logic low levels, it enables the output of the bus DB[15:0]. In serial mode, CS enables the transmission of serial data frames and outputs the most significant bit (MSB) of the serial output data one by one.

BUSY

Output busy signal. After both CONVST A and CONVST B reach the rising edge, this pin becomes a logic high level, indicating that the conversion process has begun. The BUSY output remains at a high level until the conversion process of all channels is completed. The falling edge of BUSY indicates that the conversion data is being latched into the output data register, and it becomes available for reading after a time t₄. The data reading operation performed when BUSY is at a high level should be completed before the falling edge of BUSY. When the BUSY signal is at a high level, the rising edge of CONVST A or CONVST B has no effect.

FRSTDATA

The FRSTDATA output signal indicates when to read back the first channel V1 on the parallel, byte, or serial interface. In parallel mode, the falling edge of the RD signal corresponding to the V1 result will subsequently set the FRSTDATA pin to a high level, indicating that the output data bus can provide the result of V1. After the next falling edge of RD, the FRSTDATA output returns to a logic low level. In serial mode, FRSTDATA becomes a high level at the CS falling edge because at this time the MSB of V1 will be output on DoutA. After the 16th falling edge of SCLK after the CS falling edge, it returns to a low level.

DB0 – DB15

Read data bus